VLSI Implementation of High-Performance CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphic Systems

High performance architectures for the data intensive and latency restrained applications can be achieved by maximizing both parallelism and pipelining. In this paper, the CORDIC based hardware primitives of 3-D rotation with high throughput 3-D vector interpolation are presented. The proposed architecture for 3-D vector interpolator, which is based on the redundant CORDIC arithmetic, has been implemented by VLSI and achieve up to energy saving without image quality degradation. The graphic system is power-aware. Key-Words: Redundant arithmetic, CORDIC, 3-D, vector interpolation, power-aware, high-throughput, parallelism and pipelining, VLSI.